An Investigation on Recoverable and Fault Tolarence Method-Based on Real-Time FPGA

The evolution of integrated circuit (IC) development bears witness to the challenges humanity has faced in the realm of space. Protecting ICs against sudden malfunctions due to single-event effects (SEEs) has been a paramount concern. These effects arise from the impact of a solitary particle radiation strike, such as an α-ray or cosmic ray, stemming from cosmic phenomena like solar activity and galactic events such as supernovas. This article embarks on an exploration of how SEEs have transformed alongside the advancement of complementary metal-oxide-semiconductor (CMOS) digital IC technology, particularly device scaling, spanning from the early micrometer scale generations to today’s nanometer scale iterations. In this pursuit, the study zeroes in on fundamental digital building blocks inverters and static random access memories (SRAMs). A comprehensive collection of over 100 datasets has been curated, encompassing four distinctive parameters characterizing single-event upsets (SEUs) and single-event transients (SETs) both resulting in unintended alterations of digital logic states. The study’s findings consistently reveal a trend: the scrutinized parameters, including the critical charge for SEUs, consistently diminish as device feature sizes reduce. Digging deeper, an analysis categorizing structures into bulk versus silicon-on-insulator (SOI) substrates, as well as planar versus fin channels, uncovers connections between the investigated SEE parameters and other device attributes, notably the power supply voltage. To facilitate reference and future inquiries into IC reliability, the entirety of the meticulously amassed data from this comprehensive survey is presented in a structured tabular format.