Implementation of 32-Bit Ripple Carry Adder using Binary Neural Networks for Ultra Low-Power Applications

The power consumption of digital circuits is a critical concern in the design of modern electronic systems. Binary Neural Networks (BNNs) have gained significant attention due to their ability to reduce the computational complexity and memory requirements of traditional neural networks. This paper investigates the power consumption of BNNs implemented through CMOS technology. The simulation done on 32-bit ripple carry adder demonstrate that the power consumption of BNNs implemented through CMOS technology is lower than that of traditional neural networks. The power consumption decreases as the number of layers and the size of the network decrease. Additionally, the power consumption of BNNs decreases as the input data size decreases. The paper highlights the importance of power consumption in the design of BNNs and the potential benefits of implementing BNNs through CMOS technology.