Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET

In the current state of the technical environment, power optimization, delay reduction, and leakage minimization are of the utmost importance. This is especially true as the industry works to overcome the limits brought on by scaling down to 32 nm. Through the process of designing and simulating a 14T SRAM cell utilizing 22 nm SG-FINFET technology, this study presents a fresh way to addressing the issues that are presented. This research makes use of the potential of FinFET's three-dimensional “fin” structure by adopting a configuration that is unique in that it uses 14 transistors. As a result, the study improves the stability and control of conventional 6T SRAM cells. In this work, which makes use of Synopsys HSPICE for in-depth analysis, unique voltage scaling techniques are applied within the 14T structure, and transistor sizing is optimized in order to achieve a balance between power consumption and performance that has never been achieved before. The robustness and effectiveness of this ground-breaking architecture are further highlighted by comparative and sensitivity assessments. The discoveries that were made as a result of this study not only contribute to an improvement in our comprehension of the behavior of SRAM in the era of technology with a feature size of 22 nanometers, but they also pave the way for potential future developments in low-power, high-efficiency integrated circuits.