Reversible Logic Based Asynchronous Counter in CMOS 180 Nm Technology Node Using Transmission Gate

Nowadays, low power consumption in the electronic devices is a maj or concern. In this paper present the design and implementation of a 4-bit reversible logic based asynchronous up/down counter (RL-AC) using ‘Static CMOS Logic’ (SCL) and CMOS ‘Transmission Gate’ (TG) logics. Further all the designs are simulated and compared in terms of the design metrics (DMs) such as power and area. Every circuit is designed using Cadence’ Virtuoso schematic editor using 180 nm based ‘Generic Process Design Kit’ (GPDK). The circuit simulations were carried out using Cadence’ Spectre simulator with 180nm based bsimv3v models. Further all the circuits are simulated under common Process- Voltage-Temperature (PVT) conditions. For supply voltage
$\mathrm{V}_{\mathrm{d}\mathrm{d}}=1.8\mathrm{V}$
, input signal frequency fin=250 MHz, load capacitance of
$\mathrm{C}_{\mathrm{L}}=5\text{fF}$
, the simulation results shows that the TG based RL-AC dissipates less power (1.04 mW) compared to SCL based RL-AC (1.94 mW).