A Stacked SRAM Cell with Asymmetric Threshold Voltage for Low Leakage Power Applications

When designing low-power VLSI circuits, power dissipation is one of the most difficult issues to solve. The leakage power increases as the device's size decreases. As a result, CMOS chips have a serious issue with power leakage. Submicron technology brings with it a decrease in device stability and a lower threshold voltage. When the supply voltage is lowered, the threshold voltage and oxide thickness decrease due to the increased leakage current. Several methods for lowering leakage current are studied in this research. This paper details the process of asymmetrically stacking thresholds in a Static Random Access Memory (SRAM) cell. Leakage current and energy usage are minimized because of the make use of asymmetric threshold stacked inverters in the suggested design structure. By simulating the proposed AT-S SRAM cell in the Synopsys HSPICE Tool, we found that its leakage power consumption could be reduced while its throughput on a 16 nm technology library could be increased.