Low-Voltage Flip-Flop Operation with Transition Completion Detection

A novel incredibly fast and very dependable D-flip-flop operation at low supply voltage (V
DD
) is proposed using transition completion detection (D-FF-TCD). The D-FF-TCD uses internally produced signal detection to indicate when the D-FF stage changeover is finished. By gating the pull-down strategy of the DFF stage and inferior latch, the signal used to detect disappears the decrease in operational yield, current contention, and errors with prior D-FFs. The hold duration, operating yield, consumption of energy, speed, area of existence and projected FF’s are quantifiably evaluated for a broad scope of V
DD
using the technology of 48-nm fin-FET. The D-FF-TCD's lowest VDD is demonstrated to be 570mV lower than that of earlier D-FFs, demonstrating that the D-FF-TCD can continue to drive while VDD is in the sub-threshold or near-threshold range. The D-FF-TCD functions twice as rapidly as the MSFF in terms of realistic hold time.