A 64 BIT MAC Unit Design based on FPGA Using Vedic Multiplier

The main design constraints of circuits in VLSI technology at the moment are size, electricity, and speed. The MAC is influenced by the multiplier's pace. With regular multipliers, the circuit design will operate more slowly and use more energy. The area is decreased by the recommended MAC unit by lowering the multiplier's addition and multiplication operations. The hierarchical structure of the Vedic multiplier unit allows the suggested model to operate at a faster rate. Therefore, performance of Mac may be improved by employing an effective Vedic multiplayer that has superior speed, strength, and area. These Sanskrit multipliers, which are based on Sanskrit science, are really mentioned as being among the most efficient and rapid force multipliers to expedite, Triyagbhayam, a branch of Vedic science, is used. The 64-bit MAC slows down all devices and slows down time. The MAC is created using Verilog code, and is then implemented on an FPGA board through Xilinx simulation and synthesis.