Implementing Bit Manipulation Instructions on Architecture of RISC-V Processor

A consumer electronic computing device requires a system that is effective, low-cost, low-power, highly energy-efficient, and secure. To fulfill these requirements, the RISC-V Instruction Set Architecture (ISA) has gained widespread popularity due to its support for extensive ISA extensions with specialized variants and compatibility with direct native hardware implementation. However, to enhance program runtime effectiveness and reduce power consumption in low-cost embedded-based and Internet of Things (IoT) devices, Bit Manipulation Instructions (BMIs) were developed by ARM and Intel. As a result, the learning focuses on the simplified design of the open-source RISC-V (RV32I)-based "bitRISC" processor, a fully synthesizable 32-bit CPU. This design incorporates up to 16 arithmetic and logical operations within the ISA.The "bitRISC" processor is a single-cycle processor developed using Verilog HDL and a condensed design approach. It was prototyped using the cadence tool, and power and area reports were generated and analyzed to ensure optimal performance and efficiency.