Comparative Analysis of Phase Locked Loop with Different Phase Frequency Detectors using 90nm Technology

Phase Locked Loops (PLL) are used most frequently for clock generation and clock recovery in microprocessor, networking, communication, and frequency synthesizer systems. Phase locked loops are frequently employed in high-performance digital systems to produce precisely timed on-chip clocks. Phase Locked Loop is used in contemporary wireless communication systems primarily for synchronization, clock synthesis, skew and jitter reduction. A PLL circuit with quicker locking ability is required since circuit operation speed has increased. The GHz frequency band is where many of today's communication systems operate. Therefore, a PLL with a shorter lock time that can function in the GHz range is required. Due to the PLL's architecture, it combines digital and analog signal processing units. The current study focuses on redesigning a PLL system using CADENCE Virtuoso Analog Design Environment and the 90nm manufacturing technology.A Current Starved Voltage Controlled Oscillator (CSVCO) has been taken into consideration for its superior performance in the form of low power consumption and wide tunable frequency range. In this case, develop various Phase Frequency Detectors (PFD) are Type 1 and Type 2 PFD, Charge Pump, Low Pass Filter (LPF), frequency divider, and current starved ring are used to implement the PLL, and comparisons are made. Each block's power and delay are computed, as well as the PLL's power and delay with two types of PFDs.