Efficient High-Gain Operational Amplifier Design for Σ-Δ ADCs in VLSI

This paper presents a two-stage high gain singleended operational amplifier design for Σ-Δ analog-to-digital converters (ADCs) in very-large-scale-integration (VLSI) technology. The high-gain operational amplifier design eliminates wasted drain current at the output of the operational amplifier. The first stage of the amplifier, differential pair with active load, provides high gain. The second common source stage provides a high output voltage swing. The high-gain operational amplifiers (two-stage singleended configuration) with a gain of more than 80dB and bandwidths between 3.5MHz to 5MHz have been designed and simulated using Cadence Virtuoso Analog Design Environment in 90nm and 180nm standard CMOS processes.