Enhancing the Efficiency of Wallace Tree Multipliers Through Optimized ECSLA Design

In most digital design arithmetic units, the basic building blocks are adder and multiplier. Multiplier architecture in modern VLSI circuits and digital signal processing must gain the essential parameters of high speed, low power, and small area requirements. Wallace tree multiplier is superior in its performance characteristics such as faster switching speed and requires less power as compared to other multipliers. In this paper, an 8-bit Wallace multiplier is designed using an enhanced Carry select adder (ECSLA) in four stages for the efficient addition of partial products. A multiplier is structured using the Wallace algorithm with an optimized implementation of 4-bit ECSLA in each stage to achieve a minimum propagation delay, lower power consumption, and smaller size. Each ECSLA is formalized with binary to excess-1 (BEC) logic further to meet the requirements of the current scenario. In an average of Conventional array Multipliers, the proposed Wallace tree multiplier achieved a 57% reduction in area, 88 % reduction in delay, 75 % reduction in power, and 97 % reduction in energy.