Examination of Interface Trap Charges on Electrically Doped Tunnel FET in the Presence of High-K Dielectric

In this article, we delve into a comparative analysis involving the dual material bipolar-gate electrically doped-tunnel FET (DMBG-EDTFET) and two proposed devices: the hetero-materials DMBG-ED-TFET (HM-DMBG-ED-TFET) and the high-K dielectric DMBG-ED-TFET (HD-DMBG-ED-TFET). The HM-DMBG-ED-TFET incorporates Si-Ge material at the source side and silicon on the drain and channel, while the HD-DMBG-ED-TFET employs a high-K dielectric ($\left.HfO_{2}\right)$ for its oxide layer, resulting in an observed enhancement in the ON current. However, the HM-DMBG-ED-TFET exhibits limitations in analog and RF performance, a critical concern for circuitry and radio frequency-related applications. Additionally, we explore the impact of ITCs (interface traps and charges) on these devices, aiming to address reliability issues. This investigation involves analyzing the effects of ITCs on various aspects, including electrical characteristics, linearity and distortion parameters have been carried out for low distortion and high-frequency performance investigation of the device.