Design and Evaluation of Low Power Error Tolerant Adder

Adders play a major role in signal processing and image processing applications. One of the major concerns in image processing is the amount of time taken to process the image, the size of the adder and the power consumption. All these concerns can be resolved by designing low power and high-performance adder. In this paper, inaccurate bit adder is proposed by modifying the transistor level schematic to reduce the no. of transistors. To validate the proposed adder, 16-bit carry select adder has been designed by employing the inaccurate bit adder. Inaccurate bit adder is implemented at the lower significant side of the carry select adder to trade-off the power and error rate. The energy efficiency of the proposed Error Tolerant Adder (ETA) is compared against the adders realized using the existing approximate full adders namely, Conventional Modified Approximation (CMA), Multiplexer Based Approximate Full Adder-1 (MBAFA-1), Modified Approximation-3 (MA-3), Modified Approximation-4 (MA-4). All the circuits are designed using Cadence Virtuoso® by employing 180nm CMOS process technology. Simulation results show that the proposed ETA has 75% power saving and 61% lower delay compared to the existing full adder when it is implemented on the inaccurate part of the adder.