Reversable Logic Gates Based Linear Block Codes For Multiple Adjacent Bits Error Correction

Quantum-dot Cellular Automata (QCA)is a technology that uses quantum effects to represent and process information at the nanoscale level. It is an alternative to traditional electronic circuits and offers the potential for higher computing densities and lower power consumption. Linear block codes (LBC) are a type of error-correcting code used in digital communications and storage systems. They are designed to detect and correct errors that occur during storage or transmission of data. However, the complementary metal-oxide-semiconductor (CMOS) based LBC designs are consuming higher area, delay, and power. So, this work implemented the reversable logic gates (RLG) based LBC (RLG-LBC), which operate on binary data and are defined by a generator matrix and a parity-check matrix. Initially, the RLG based LBC encoder is generated using Feynman gate, and Peres gate. These two gates are used to develop the parity bits for the RLG-LBC encoder. Then, the error occurred RLG-LBC encoded data applied to RLG-LBC decoder, where syndrome decoder checks the bitwise adjacent errors. Finally, the error correction network corrects all bitwise errors through syndrome values, which generates the error free output. The simulation outcomes show that, the proposed RLG-LBC resulted in reduced area, delay, power consumptions as compared to other encoding methods.