Design and Evaluation of a 4-bit ALU and RAM System: A Step towards Ultra-Low Power Computing

This conference paper presents the design and implementation of a low-power 4-bit Arithmetic Logic Unit (ALU) with a Random-Access-Memory (RAM) module on Cadence platform. The proposed ALU architecture aims to address the growing demand for energy-efficient processors in modern computing systems. In this work, we leverage advanced low-power design techniques to optimize the ALU's static leakage power by around 66.24% while ensuring minimal performance degradation. The design uses minimum required transistors with power gating to reduce dynamic and static power dissipation. Power Gating is performed by shutting down the power for a portion of the design in order to reduce the static(leakage) power in the design. Furthermore, we introduce an integrated RAM module within the ALU architecture to enhance overall data handling capabilities and minimize data access latency. The RAM is carefully designed to consume minimal power during read and write operations, contributing to the overall energy efficiency of the ALU. The proposed design is simulated and validated on the Cadence platform to assess its performance and power characteristics. The simulation results demonstrate significant improvements in power efficiency compared to conventional ALUs without compromising on critical performance metrics. Moreover, the integrated RAM module showcases notable gains in data handling and access speed. In conclusion, the presented low-power 4-bit ALU design with an integrated RAM module on Cadence offers a promising solution for energy-conscious computing systems.