A Novel Non-Volatile SRAM with Reduced Read Delay

Static Random Access Memories (SRAMs) are well known for their ability to operate at high speeds. However, their performance is constrained by their volatility. Any standard SRAM can be altered into a non-volatile SRAM by placing a non-volatile memory (NVM) device within the cell. In this paper, we present a new non-volatile SRAM that was designed and simulated in LTSpice using the 32nm Predictive Technology Model (PTM) from Arizona State University. Our proposed circuit not only demonstrates improved read delay but also boasts low power consumption. We evaluated various parameters of the proposed circuit, including non-volatility, static noise margin (SNM), and read and write delay.