Research of Chip Placement Accuracy for Fan-Out WLP Using A Novel Self-Assembly Stage

This paper discusses the alignment accuracy after self-assembly using a novel self-assembly method with a uniquely developed porous stage. In a preceding paper, we have introduced our process that combines tape expansion technology and self-assembly technology. By using this process and machine device, it is possible to significantly improve the throughput of pick and place process for FO-WLP. Furthermore, it is indicated that our self-assembly method using the porous chuck stage enables achievement of high precision chip alignment and high throughput. In this study, two factors are evaluated to clarify the impact on the chip accuracy after self-assembly; 1) the influence of chip position before self-assembly, 2) the relationship between stage size of self-assembly area and chip size. As a result of evaluation, if the chip size is the same as the porous stage size, the alignment accuracy after self-assembly is within 5 μm or less even with varied chip positions before self-assembly. On the other hand, when the porous stage size and chip size are different, the chip position before self-assembly has an impact on the alignment accuracy after self-assembly. Based on the results obtained in this study, further development of machine device and process will be pursued to improve the alignment accuracy after self-assembly.