DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis

High-level synthesis (HLS) is becoming increasingly popular in hardware design. However, since current HLS tools are not fully verified, the semantics of a desired high-level design and the actual behavior of the HLS-generated hardware might be different, causing a functional discrepancy. Existing solutions locate functional discrepancies by adding checkpoints into the Internal design, but they do not treat resource usage as a hard constraint. In this work, we propose a graph-based method, called DiffLo, which considers 1) coarse-grained localization effectiveness, 2) fine-grained localization effectiveness, and 3) resource usage, to selectively and analytically add checkpoints into the design under a resource constraint so that HLS users can reduce their effort to locate the portion in the high-level source code that relates to the functional discrepancy. Our experiments on our real example and the CHStone benchmarks show that the proposed method can significantly reduce the effort required for functional discrepancy localization.