A Highly Pitch-Scalable Capacitor-less 3D DRAM Using Cross-bar Selection with Gate-Controlled Thyristor (GCT) Featuring High Endurance and Free Read-Disturb

We substantially enhanced the 3D DRAM GCT [1] device by incorporating the principles of cross-bar array selection. The GCT device provides ideal self-rectifying I
BL
-V
BL
curves with super steep slope at forward break-over voltage of 1.7V, large ON/OFF ratio >1E6 at read, and ultra-low leakage current <1pAper cell at reverse read. It therefore enables efficient cross-bar selection for a large-density array due to its low background leakage. The "Program" operation involves applying a high BL bias (>=1.9V) over the threshold, while "Read" operation entails applying a low BL bias (<=1.5V) below threshold. The GCT device latches up the gate-controlled "PNPN" diode after program, and exhibits no read disturb during continuous read operation lasting 10,000 sec. The multi-gate (three) WL biases remain fixed during read/program operations to facilitate a simple design. The WL bias is only changed during sector erase. This cross-bar selection technique enables vertical-BL 3D DRAM for improved sensing while allowing for practical processing with loosely spaced staircase contacts on the source line. The WL’s are shared vertically and laterally, enabling aggressive X/Z pitch scaling without facing the challenges of vertical-gate 3D DRAM. It is estimated that this 3D GCT DRAM is suitable for dimension scaling below 10nm. We have verified the feasibility of array selections for read, program, and erase in both selected and unselected sectors. The GCT device shows promising potential to realize simultaneous pitch scaling and high-layer stacking for 3D DRAM. It demonstrates high endurance >1E10 (measured, and projected to be infinite), and holds good potential to realize DRAM-based computing in memory (CIM).