Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

For the first time, a comprehensive guideline is proposed for a gate stack design of ferroelectric vertical NAND (Fe-VNAND), based on in-depth analytical modeling and experiments. Based on the guideline, the metal-insulator-ferroelectric (FE)-insulator-silicon (MIFIS) gate stack has been demonstrated, showcasing its benefits in all three aspects of reliability (endurance, retention, and disturb characteristics) and its potential for wide memory window (MW, 5.5 V and above), as well as compatibility for VNAND processes.