SEE characterization of Microchip RTG4 FPGA SerDes block and GRLIB SpaceFibre IP core

This work presents an independent SEE characterization of the on-chip high-speed SerDes interface of Microchip’s RTG4 Flash-based FPGA while running GRLIB’s SpaceFibre IP core. The results obtained show an overall SEE rate of $2.4\times 10^{-5}$ and 6.4$\times 10^{-6}$ events/device/day for typical GEO and LEO orbits, respectively, and an average auto-recoverable rate of the GRLIB’s SpaceFibre IP core of 94%.