Digital Twin for Gate-Resistor Optimization of Parallel, 100 V, 7 mΩ, GaN HEMTs based on Comprehensive Multi-Domain Simulations and Physically-Motivated Transistor Models

By utilizing a digital twin, based on physically-motivated device models and comprehensive time and frequency domain simulations for parasitic extraction, in this work a gate-loop resistor optimization utilizing paralleled 48V, 7mΩ GaN HEMTs in a buck-converter for a 300 kHz, 48V to 24V, high current DC/DC operation up to 80A is presented. Through automated transient simulation and evaluation of both overshoots and switching losses of all four GaN HEMTs, all gate-resistors R
g,on–HS
, R
g,off–HS
, R
g,on–LS
, R
g,off–LS
are optimized individually for maximum efficiency or minimal drain and gate voltage overshoots at the switching transients, to extend the life-time of the transistors and minimize device failures and breakdowns. The simulation includes the main parasitic components (power and gate loop inductances), derived from a full-wave electromagnetic simulation up to 3GHz of the assembled PCB, which are crucial for the converter performance and digital twin fidelity. The overshoot-optimized version is resulting in a 35% reduction of the low-side turn-on overshoot with only 0.4% lower efficiency (96.7% instead of 97.1%) at 60A for the efficiency-optimized version. The approach of this work is a promising basis for further optimization with a useful combination between system-level and device-level simulations, necessary for the evaluation of fully automated syntheses of power electronic sub-systems, as well as the evaluation of design spaces.