A Deep Neural Network Translator for Edge Site Implementation

Implementing deep learning models (DNN) on edge sites remains challenging. Besides the high complexity of DNN models in their architecture, programming directly in hardware languages requires high-level verification to render these models run on edge devices. By utilizing High-Level Synthesis or HLS technology to generate HDL (Hardware Description Language) containing the DNN model, in this study, we built a DNN translator. DNN translator translates the model and its weights from the Pytorch-based DNN model to C++. The generated C++ files can be synthesized using HLS tools such as Vitis HLS or Vivado HLS. HDLs resulting from the synthesis of generated C++ are provided with HLS Pragmas to optimize the design. This DNN translator provides a solution to expand the application of the DNN model to edge devices, especially FPGA, as one of the potential edge devices. In the implementation, our DNN translator successfully generated C++ files for synthesizing the Multi-layer Perceptron (MLP) and LeNet5 and implemented them in an FPGA, Arty A7-100.