Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals

In recent years, FPGAs have been used in many IoT devices and are equipped with cryptographic circuits to ensure security. However, they are exposed to the risk of cryptographic keys being stolen by side-channel attacks. In this study, we conduct simulation experiments of power analysis attacks on AES circuits and clarify the correlation between the sampling interval and the amount of leakage of side-channel information. T-test is used to evaluate the amount of leakage, which is based on four metrics. Experimental results show that the detailed sampling interval is more strongly correlated with the amount of side-channel leakage than the clock period of the circuit.