FPGA implementation of energy efficient Vedic multiplier using CSA architecture

This research presents a comprehensive differential analysis of 32-bit Vedic multipliers employing distinct adder types namely, RCA, CLA, and CSA. The underlying Vedic multiplication methodology utilized in this study is the Urdhva Tiryagbhyam method, renowned for its efficiency and speed. In this study, we harness the power of Vedic Mathematics to design 32-bit multipliers and examine their behavior when coupled with different adder architectures. Our research focuses on comparing the efficiency of three distinct adder architectures in the context of 32-bit Vedic multipliers. The RCA, CLA, and CSA adders serve as the core components of our multiplier designs. The Urdhva Tiryagbhyam method from Vedic Mathematics forms the basis for multiplication operations. Through extensive simulations conducted using the Xilinx software platform, we scrutinize the performance of each multiplier configuration. Key performance metrics, including speed, power consumption, and area utilization, are evaluated to provide a comprehensive understanding of their comparative advantages and disadvantages. The insights gained from this comparative analysis have significant implications for the design and optimization of multipliers in digital computing systems.