Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis

Globalization of the Integrated Circuit (IC) supply chains have resulted in security vulnerabilities especially with potentially untrusted third-party manufacturing facilities. Split Manufacturing has been shown to provide defense against some of these vulnerabilities. Nonetheless, split manufactured designs are subject to attacks such as the Network Flow Attack, that has attempted to reconstruct the missing BEOL (Back End Of Line) signals. Therefore, it is crucial to select the BEOL signals carefully. Although several defense strategies have been proposed to provide protection to the design against these attacks, most of them have been implemented at the logic and layout levels that require expensive re-synthesis cycles. In this paper, we propose a secure BEOL signal selection method at a higher abstraction level, based on prioritizing Data Flow Graph edges by assigning edge-weights during scheduling and allocation stages of high level synthesis. Our method decreases the attack correctness with increase in the percentage of edges lifted and has minimal impact on design performance in terms of the total routed wirelength.