RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks

Functional reverse engineering of flattened Field Programmable Gate Array (FPGA) Look-Up Table (LUT) netlists to Register Transfer Level (RTL) representation is essential to understand, reconstruct and enhance the existing legacy designs. Recent advances in machine learning show promising results in solving EDA problems. In this paper, we propose a tool, RELUT-GNN that uses Graph Neural Networks (GNNs) to extract high-level functionality of data path elements from LUT-level netlists. For GNNs, the netlist structure is represented as a graph with FPGA leaf cells as nodes and the nets among them as edges. We extract features for each node and train the GNN to learn the structure of the netlist by aggregating their node features and their neighbors. The training dataset includes a comprehensive custom dataset consisting of various Operators, Shifters, Counters, FSMs, and their combinations of varying bit widths. The model is validated and tested on unseen real-world designs obtained from Opencores and ITC99. It is observed that RELUT-GNN achieved a combined accuracy of 97.12% for the classification of selected benchmarks from arithmetic and DSP cores and the ITC‘99 benchmarks.