A Two-Step SAR Capacitance-to-Digital Converter

The design of a two-step successive approximation register (SAR) capacitance-to-digital converter (CDC) is presented. First the coarse conversion stage performs a capacitive offset compensation down to within 10fF. The fine conversion stage converts the amplified residue voltage with a resolution of 200aF. Repeated fine conversions occur until an out-of-range condition arises. These bits are communicated off chip on an I
²
C bus. The effective number of bits (ENOB) is compared for sinusoidally varying capacitance inputs. The circuit achieves 9 ENOB with a 28μs conversion time under nominal conditions and 8.2 ENOB with
$14\mu\mathrm{s}$
conversion time when overclocked. This equates to an ENOB throughput of 321kbits/s and 585kbits/s, respectively.