Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis

SAT-based exact synthesis is a powerful technique, which enables synthesizing reconfigurable circuit that only relies on a gate-level operator switch. However, its runtime behavior can be unpredictable and slow. In this paper, we propose fence initialization and update methods for exact synthesis to substantially accelerate the simulation to find the valid circuit topology for function-switchable reconfigurable logic circuits. According to the simulation results from disjoint-support decomposable (DSD) benchmarks, the proposed algorithms obtain a significant runtime reduction of up to 95.1% with up to 31.4% reduction in logic depth.