Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches

Neuromorphic systems can benefit greatly from using quasi-delay-insensitive (QDI) asynchronous interconnection networks, which can improve power consumption, robustness, and scalability. Contemporary asynchronous circuit designs use standard multiplexer cell-based switches, which can lead to area overhead and increased power consumption when designing Networks-on-Chip(NoC) routers, especially high-radix crossbar switches. To overcome these ignored challenges, we propose two solutions: a coarse-grained design approach for NoC router switches, and a fine-grained design approach for high-radix crossbar switches. Coarse-grained approach in designing asynchronous switches for NoC router switch resulted in a 36% reduction in transistor count, 77% reduction in power consumption, and 18% improvement in delay against contemporary multiplexer-based designs. Fine-grained approach to designing asynchronous high-radix crossbar switch resulted 56% reduction in delay. We have implemented the transistor-level switches using the Sense Amplifier Half-Buffer (SAHB) logic family and have evaluated its performance using spice models for 65-nanometer CMOS technology.