A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC

This paper presents an 8-bit cyclic Vernier digital-to-time converter (DTC) for time-mode successive approximation register time-to-digital converters (SAR TDCs). The DTC offers a low degree of mismatch-induced nonlinearity hence a small lower bound of the dynamic range, a virtually unlimited upper bound of the dynamic range, and a small silicon area. The principle, operation, design, and calibration of the DTC are presented. The DTC is designed in TSMC 130 nm 1.2 V technology and analyzed using Spectre with BSIM3v3 device models. Simulation results show that the DTC achieves a dynamic range of 2.31 ~ 591.4 ps, a DNL of 0.37 LSB, an INL of 0.66 LSB, and consumes 1.49 mW.