Design Evaluation and Performance Prediction of Different SRAM Cell Topologies through Inverter Optimization for the 5nm Technology Node using GAA CNTFETs

This research paper focuses on optimizing a 5nm node carbon nanotube field-effect transistor (CNTFET) based inverter while considering the trade-off between performance and stability and comparing it with a 32nm CNTFET inverter. Alongside size optimization, the model parameters of the CNTFET, such as diameter, flat band voltage, and density, are evaluated and calibrated to amplify the performance and stability of the CNTFET inverter. The optimized CNTFET inverter is then employed in designing various static random access memory (SRAM) cell topologies, including the conventional 6T SRAM and 7T, 8T, and 9T SRAM cells. Our optimized 6T SRAM is compared with existing 5nm node CNTFET, GAA MOSFET, SOI-FinFET, and S2N based 6T SRAM cells present in the literature, and we find that our cell outperforms its counterparts in the metrics for stability and delay. A comparative evaluation is conducted to assess the performance of different CNTFET-based SRAM cell topologies using performance metrics such as static noise margin (SNM), delay, and leakage power. The findings indicate improved stability and performance of the SRAM cells, despite an increase in the cell area, leading to an overall enhancement in system performance.