Methodology for Timing Closure in VLSI Physical Design containing high clock to Q Memory Delay

Timing closure in VLSI physical design is the most basic, as well as important task. For macro dominant designs we often see memories have high tcq delay which makes timing closure very difficult and tedious job. In this paper we have discussed that, due to large tcq delay of custom IPs also known as macros or memories it is very difficult to achieve positive slack for memory to register paths. Even if the paths have very minimal combo logic sitting between memory and register , due to the large memory delay, a large part of time period is consumed by memory, leaving very less time for other logics, resulting in failing of slack. We have introduced a methodology called mem to reg attraction in which, with the help of TCL scripting we are identifying the first level register connected to the pins of macros and placing it near it. With this we are decreasing the interconnect length and in turn interconnect delay is reduced, resulting in increasing the chances of meting memory to register timing. The experiment is been conducted in Cadence® Innovus™ Implementation System which is A Physical Design Implementation tool for high-density designs at advanced and established process nodes in 5nm design node. Later the results and outcome showing significant improvement is been discussed.