Sampling Delay Effect on Stability in Digitally Current Mode Controlled Flyback Converters

Digital current mode control (DCMC) is often used in flyback DC-DC converters to achieve fast transient and high efficiency without transformer core saturation. Continuous-time (CT) small-signal models are traditionally used to design DCMC; however, such models are insufficient to predict fast-scale instability that may occur due to the sampling delay while using higher controller gains in achieving higher closed-loop bandwidth. In this paper, a unified discrete-time (DT) modeling technique is developed to derive both the DT large-signal and small-signal models by considering practical sampling delays under interval-1 and interval-2 sampling techniques. Large-signal models are validated using SIMPLIS simulation. The effects of sampling delay and the RHP zero are analyzed. Closed-loop stability boundary is accurately predicted. The design steps are presented to achieve fast transient with stable periodic behavior. SIMPLIS simulation case studies are presented to demonstrate the usefulness of the proposed DT modeling framework using a 36 V/380 V 300 W flyback converter. The proposed framework is useful to design stable digital control with fast transient response.