Design of Maximally Flat and Higher Drain Efficiency Mode Class F Power Amplifier for 2.4 GHz Applications

Due to the requirement of fast switching driver signal and active device larger switch stress, class E non linear power amplifiers are not fitted for low power and lower breakdown voltage present trend wireless applications. Class F power amplifier fulfils these requirements with easy implementation and better integration with CMOS sub micron technology. This proposal presents the simplified design procedure of class F power amplifier in maximally flat efficiency and maximum drain efficiency modes. The FET transistor amplifier with $3^{rd}$ and $5^{th}$ order odd harmonics has been simulated using Advanced Design System (ADS) software and theoretical and simulated efficiency values have been compared. At 2.4 GHz, the output power, drain voltage, drain current, and efficiency variation for maximally flat and maximum drain efficiency modes has been studied for the class F power amplifier. The MATLAB design based efficiency calculation has been properly matched in ADS simulation and higher efficiency has been achieved for higher order harmonics in the maximum drain efficiency mode of operation.