Improvement In Thermal Issue By Using Suitable Dielectric Material And Core For Future IC Integration Applications

The technological and economic problems of dimensional scaling, as well microelectronics' growing connection delay, have influenced the development of three-dimensional integrated circuits throughout the last few decades. Vertical integration of numerous transistor planes in a 3-D IC, either monolithic or by joining multiple stratums, provides reduced connectivity time and improved design freedom. On the other hand, the vertical integration of a 3-D IC poses considerable thermal management difficulties. The circuit's heat distribution is erratic and unreliable. Hot spots are easily created by the superposition of power consumption in each layer, which has a negative impact on the chip's performance. This study suggests employing thermal through silicon vias (TTSVs), which move heat to a sink as they descend, to remove heat from between the IC layers. Fins can be used (i.e., taking into consideration the orientation, width, and material of the fins) in combination with choosing the best TSV proportions to achieve the greatest possible thermal conductivity with the least amount of density, which enhances chip performance.