A New Single Phase Latch-Mux Based Dual-Edge-Triggering Flip-Flop For Low Power Applications

In order to meet the growing demand for energy-efficient devices, particularly in portable and battery-powered applications, low-power flip-flop designs are crucial in modern electronics. In this work, a novel design for single phase clock dual-edge-triggered (DET) flip-flop is presented. In comparison to the existing state-of-the-art designs, the proposed design uses a single transistor-clocked buffer to overcome redundant transition power with less area. The design is simulated using 18nm FinFet technology. In comparison to the existing designs, the proposed design performs better in terms of power (21%), area (33%), and power delay product, PDP (26%) for various switching activities.