Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites

The adoption of Machine Learning solutions directly onboard in satellite missions is becoming more and more attractive for the space sector. Among the various kinds of hardware accelerators, ranging from highly efficient yet inflexible COTS to more versatile FPGA-based solutions, Coarse-Grained Reconfigurable Array architectures are gaining importance in the field. CGRAs find applications in various domains, including digital signal processing, image and video processing, and cryptography, thus being considered also for space-related applications. They comprise an array of Processing Elements, whose complexity is between FPGA logic cells and general-purpose processors, interconnected through a Network on Chip. They excel in handling data-flow graphs and can be more efficient than FPGAs for the execution of specific tasks. Their versatility hinges on various architectural aspects of the coarse-grained array of Processing Elements. Among them, the supported operations, the possible interconnections, and the pipeline stages impact the functionality, the area, the power consumption, and the maximum frequency of the accelerator. In this work, we present a highly parameterised CGRA-based accelerator that we developed for an extensive Design Space Exploration on these architectures. The description starts from the CGRA building blocks, the Functional Units, and progresses towards the top level of the architecture, represented by the Node component, which is composed of an NxM matrix of Processing Elements. For each level of the hierarchy, we describe the HDL design parameters affecting the run-time reconfigurability of the accelerator, delving deeper into the functionality of the architecture. In the last section, we present synthesis results on the 40nm Standard-Cell technology from TSMC, highlighting performance, power consumption and area occupation for many different combinations of design parameters.