A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler

This paper proposes a pulse amplitude modulation-4 (PAM-4) baud-rate clock and data recovery circuit that improves phase detector (PD) gain by increasing transition density. The proposed idea is that one sampler (shared sampler) serves as a data sampler and an error sampler simultaneously to minimize the number of samplers. It can reduce power consumption while having a high phase detector gain. In addition, the accuracy of the early/late signal is improved through the pattern dependent phase detector. Simulation result shows power consumption of the proposed receiver is 0.79[pJ/bit] at -17.8dB channel loss. This work is designed using 65nm process.