Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect

In this paper, we designed and analyzed multi-stripline M1 redistribution layer (RDL) interposer channel for high bandwidth M2 memory (HBM) module considering full channel routing feasibility and via interconnect structure. Electrical performance of RDL M3 interposer channels were analyzed in terms of insertion loss and far-M4 end crosstalk (FEXT), and verified with eye diagram simulation based on driving conditions of HBM3. Simulation results show high insertion M5 loss and FEXT occurring at M4 layer, due to discontinuous reference plane at RDL transition via, and increased timing jitter at eye diagram. By placing ground vias near M4 RDL transition via, overall electrical performance was significantly improved. As a result, it showed that RDL transition via and ground via placement should be considered when designing multi-stripline RDL interposer channels.