Method and Module on FPGA for Parallel Unification of Predicates

To solve the problem of increasing the performance of inference machines, the authors propose to use parallel methods for implementing the basic knowledge processing operations and a specialized device based on modern FPGAs. The block of parallel unification was designed in CAD Quartus II, and the prototype of the block was implemented on the Cyclone IV FPGA. The experiments carried out showed the correct operation of the unit and a significant increase in its performance.