An Accurate Area Model for FPGA Circuits at Advanced Technologies

As the process technology is constantly evolving, the pitch definitions and design rules of advanced technologies are more aligned with standard cell library development. To adapt to complex design rules and receive better variability control, a definite trend of circuit design is a greater proliferation of cell-based design. Based on the cell-based design method, FPGA transistor-level sizing tools are used for FPGA circuit design and architecture exploration, where the area model provides area estimates of FPGA circuitry. The accuracy of the area model strongly impacts the quality of results for circuit optimization and architecture exploration. However, current area models are not accurate enough under the advanced technologies and cell-based design method. A new area model is proposed in this paper to quickly and accurately estimate the layout areas of standard cell-based FPGA circuits. Based on the spice netlists of FPGA circuits, the proposed area model fully considers the source-drain sharing characteristics of the layout implementation and provides accurate area evaluation results. We validate the area model by comparing it with the areas of actual cell-based FPGA circuit layouts. The experimental results show that the deviation between the proposed area model and the actual layouts is within 4.44%, and 0.18% on average. It is more accurate than the widely used minimum-width transistor area model and its variant.