A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC

This paper presents a low jitter multiplying delay-locked loop (MDLL) with a current-controlled delay line (DL) for high-precision time-to-digital converter (TDC). A multiphase clock with uniform distribution generated from the delay line is applied directly to the high-precision TDC. To achieve better performance output phase splitting, a voltage-to-current circuit (VTC) is introduced to extend the locking frequency range and enhance frequency tuning linearity of MDLL. Additionally, to decrease the phase noise in the locked state, an improved charge pump (CP) with matched switches is utilized to improve the match between charge and discharge currents. The improved reverse differential delay cell structure can suppress the common mode noise in the delay line, which is used to improve the resolution of TDC. This paper uses 180nm CMOS technology to realize a MDLL with an output of 65MHz-325MHz, occupying an area of 0.084mm2. The simulation results show that the total power consumption of the chip core is 9.41mW@200MHz under 1.8V power supply, the locking voltage is 820mV when the MDLL loop is stable, the RMS jitter is 1.73ps@200MHz, and the standard deviation of each 45° adjacent phase interval is less than 1.5ps.