Design of Multi-Mode Digital Signal Processing Circuit for Digital Transmitters

This paper presents a multi-mode digital signal processing circuit supporting LTE and 802.11ax standards. It introduces an up-sampling module based on the Farrow structure with configurable interpolation multiples, which can convert the sampling rate of output data to the frequency that is integer-divided from the carrier frequency so as to avoid output fractional spurs. At the same time, a high-efficiency automatic error-correcting μ value generator is used to improve the precision of the fractional up-sampling module. Moreover, the digital signal processing circuit also uses integer multiple interpolation and filtering technology to further improve the signal sampling rate, signal-to-noise ratio (SNR), and anti-aliasing capability.