A Bang-Bang Phase Detector for PAM-N Signaling

Phase detector design for clock and data recovery (CDR) becomes challenging as the number of pulse amplitude modulation (PAM) levels increases. This paper presents a bang-bang phase detector (BBPD) architecture for PAM with N-level signaling (PAM-N) that balances the complexity and performance by utilizing an edge slicer whose threshold is adjusted according to the types of transitions. To accommodate high-speed applications, one-eight-rate architecture with carefully chosen timing is exploited. The validity of the proposed BBPD is examined for its PAM-4 and PAM-6 versions in 28 nm CMOS technology.