A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation

With the rapid advancement of deep neural networks, the automatic generation of accelerator design is a very important problem for the deployment of AI applications, especially for edge computation. In this paper, we propose a general purpose compiler design for instruction-based CNN accelerator design. Our compiler incorporates network pruning and quantization capabilities for better performance. CDFG-based layer fusion and scheduling are used for heterogeneous computing with consideration of data transformation and synchronization between CPU and accelerator. A device file is used to define the instruction set and data space so that our compiler supports various accelerator designs uniformly. We used our compiler to implement VGG16 and yolo2 in FPGAs and achieved better performance than existing designs.