Power Optimization in 6T-SRAM Cell using Carbon Nanotube Field-Effect Transistors (CNTFET)

Due to their superior performance, dependability, and low power consumption, carbon nanotube field-effect transistors (CNFETs) have become a silicon-free alternative to static random-access memory (SRAMs). A six-transistor CNTFET-based SRAM (C-SRAM) cell loses Power during inactive periods. This investigation proposes a voltage divider method and a power-down transistor method to reduce SRAM leakage power. HSPICE simulation determines the optimal channel length for the best low-power and high-performance performance. In Nanoscale technology, the percentage of total Power consumed by leakage is rising-a low-power C-SRAM cell to combat the power leakage problem. At the 32nm manufacturing node, HSPICE's CNTFET was used to simulate a 6T SRAM cell architecture using the Stanford CNFET model. The proposed step-down transistor method reduced leakage power by 38.4% and decreased delay by 9%, whereas the voltage divider method reduced leakage power by 19.3% and decreased delay by 4%.