Implementation of an Array Multiplier Using an Addition Algorithm with Signed Digit Representation

Nowadays technology has widely been developed and has expanded to a large extent so that the digital computing is widely used for various applications and this need has demanded for the introduction of various number system representations in the digital world. We know that many operations like multiplication, division etc. need the use of repeated addition operations widely. When it comes to digital arithmetic operations like multiplication and division, where addition is the main operation involved. Here the carry propagation depends on the operand length. When carry propagation increase, the delay of the circuit also increases and require a high complex circuit. The multiplication operations may thus tend to take up more time and the delay of the system may increase. The Binary Signed Digit (BSD) number system is used to thus speed up the operations. One main advantage of BSD adder is that it will eliminate the carry propagation, thereby improving the efficiency of the system. Using this addition algorithm. It is expected to reduce area utilization and increase speed. So the aim of the proposed system is to implement an Array Multiplier using this addition algorithm to improve the speed and area utilization when multiplications are carried over. Thus, faster multiplications will be achieved.