Implementation of a Clock Synchronization Chip Based on Time-to-digital and Digital-to-time Converters With a Shared DLL for Chip-Scale Atomic Clock

This brief presents a fast-coarse and fine two-level combined architecture of Time-to-digital Converter (TDC) and Digital-to-time Converter (DTC) based on a shared Delay-locked loop (DLL). The fast-coarse measurement and coarse synchronization strategy adopted in the coarse TDC/DTC can greatly shorten the measurement and synchronization time. The fine TDC/DTC share a voltage control provided by DLL, which can effectively save area and power consumption. The prototype circuit is designed and fabricated in the SMIC 0.1S$\mu$m CMOS process. The presented circuit realizes an approximate 16.44-ms precise measurement range and an extended l-s maximum dynamic range. With a 2.0 mW of power and silicon area of 0.326 $\mathrm{mm}^{2}$, the presented circuit as an IP has been integrated into a system on-chip (SoC) for Chip-Scale Atomic Clock (CSAC), which can facilitate the development of the miniaturization and low power consumption of CSAC.