Design of Efficient Approximate Adders for Error Analysis and Mitigation

Numerous compute-intensive algorithms are used for low-energy and high-speed circuits. Approximate computing is an alternative approach that can be employed in error-tolerant applications like audiovisual processing. For low-energy and high-speed circuits, numerous computationally expensive algorithms are used. An alternate strategy can be used in error-tolerant applications like audiovisual processing is approximate computing. In this study, lower logic complexity-based approximation full adder designs are proposed with the goal of reducing latency and energy consumption at the cost of introducing some errors at the output. The proposed and referenced approximate adders are designed in the Verilog HDL language. All adders have been simulated and synthesized by Xilinx Vivado software. The proposed designs show lower logic complexity, low power consumption, and improved error matrix calculations.